Operation via Ethernet/OPC UA
With a high CPU load, e.g. during a parameter set change, there is
the danger that no FIFO entries are made. Also the time channel
could then contain wrong values, since the counting up of the milli-
seconds in the time channel is also omitted in this case.
You can start a continuous recording or choose between two variants for trigger-
controlled recording:
1. Status-controlled filling of the FIFO.
The bit mask of the digital flags determines the filling, see
of I/O flags (I/O status)" on page
if at least one of the bits is set and an active difference condition is fulfilled
(see Mode of Operation).
2. Edge controlled filling of the FIFO.
The bit mask of the digital flags determines the filling, see
of I/O flags (I/O status)" on page
each of the 6 possible signal sources if one of the bits changes and an
active differential condition is fulfilled. With this function, in contrast to the
other mode of operation, the change of only one bit from High to Low or
from Low to High with several already active bits (High) is also recognized
as a trigger.
You also have the following options
1. You can specify that a specific difference from the last stored value must be
exceeded.
As soon as the difference value between the last value stored in the FIFO
and the current value at one of the 6 signal sources is exceeded, the current
value of all signal sources is written to the FIFO memory. All 6 difference
values have to set >0 so that the difference trigger is being activated, see
General and System Objects: FIFO.
2. A command can be used to make a single entry for all FIFO channels (sig-
nal sources).
The time of the command is used as the start time (current date and time
and time channel = 0). A running recording will be restarted, but the FIFO
memory will not be deleted. A recording that is still running should therefore
114
162. Filling is active if the result is not 0, i.e.
162. 1 measured value is recorded from
A04643_04_X00_03 HBM: public
"Digital flags: List
"Digital flags: List
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