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Aim-TTI PL-P SERIES Bedienungsanleitung Seite 21

Programmable power supplies
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Bit 3 -
Bit 2 -
Bit 1 -
Bit 0 -
Limit Event Status Register and Limit Event Status Enable Register
These two registers are implemented as an addition to the IEEE std.488.2. Their purpose is to
allow the controller to be informed of entry to and/or exist from current limit by any outoput.
Any bits set in the LImit Event Status Register which ocrrespond to bits set in the Limit Event
Status Enable Register will cause the LIM bit to be set in the Status Byte Register.
The Limit Event Status Register is read and cleared by the LSR? command. The Limit Event
Status Enable register is set by the LSE<nrf> command and read by the LSE? command.
Bit 7 -
Bit 6 -
Bit 5 -
Bit 4 -
Bit 3 -
Bit 2 -
Bit 1 -
Bit 0 -
20
121
minimum set voltage value for output 1 exceeded.
122
minimum set voltage value for output 2 exceeded.
123
minimum set voltage value for output 3 exceeded.
131
minimum set current value for output 1 exceeded.
132
minimum set current value for output 2 exceeded.
133
minimum set current value for output 3 exceeded.
141
maximum delta volts value for output 1 exceeded.
142
maximum delta volts value for output 2 exceeded.
143
maximum delta volts value for output 3 exceeded.
151
maximum delta current value for output 1 exceeded.
152
maximum delta current value for output 2 exceeded.
153
maximum delta current value for output 3 exceeded.
200
byte value was out of range.
Operation Time-out Error. Set when an attempt is made to set an output to a
specific voltage value, with verify specified, and the output Volts do not settle
within 5 seconds. this can happen if, for example, a large value of capacitance
exists across the output and the current limit is set to a very low value.
Query Error. Set when a query error occurs. The appropriate error number will be
reported in the Query Error Register as listed below.
1
Interrupted error
2
Deadlock error
3
Unterminated error
Not used.
Operation Complete. Set in response to the ∗OPC command.
not used.
Set when output 3 enters voltage limit.
Set when output 2 enters voltage limit.
Set when output 1 enters voltage limit.
Set when output 3 over voltage trip has occurred.
Set when output 3 enters current limit or foldback.
Set when output 2 enters current limit.
Set when output 1 enters current limit.

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