Inhaltsverzeichnis
Werbung
Verfügbare Sprachen
Verfügbare Sprachen
•
Smartcard port - the main smartcard driver port (SC0x) is used to carry all the low level controls for the CA (Conditional
Access) smartcard – reset, clock, data I/O, etc. These lines are protected by resistor / diode networks (R257 - R262,
R266, D201- D206, D209) and linked to the smartcard PCB which is mounted in the analogue section through PL204.
The CPU has a number of parallel port pins which are used to control various functions on the COFDM and MPEG PCBs,
these are:
Port Identification
GP1040
GP1041
GP1042
GP1043
GP1044
GP1045
GP1046
GP1047
GP1048
GP1049
•
Local CPU memory control
•
Internal cache – this is internal to the CPU
•
DRAM control – the CPU has a dedicated control interface for the main DRAM. Addressing for 16Mbit (IC201) is provided
and EDO type DRAM is used.
Address decoding within CI A (based on CS2) allows access to the 'CS miss' devices for which the chip selects are generated in the
CI A device, the timing for these data communications is then provided using the DSACK controls.
For functional reasons each interrupt group is made up of a pair, each representing an internal and an external input (12 into 6
levels), each interrupt pair is assigned a group, and the groups are prioritised. The system interrupts are allocated as follows:
Group
Function
External INT 4 / Internal NMI
4
Timer (0-2) / RES
3
External INT 3 / PID processor
2
External INT 2 / Teletext / I2C / UARTS
1
External INT 1/ Smartcard
0
External INT 0 / 1284
External Interrupts are mapped as follows
•
EXTERNAL INT 4:External DRAM controller
•
EXTERNAL INT 3:Common Interface B
•
EXTERNAL INT 2:1394
•
EXTERNAL INT 1:Common Interface A
•
EXTERNAL INT 0:A/V Decoder
Note: The external interrupts have been re-arranged to enable debug on IRQ 4 while the DRAM controller is not being fitted.
The internal memory map is as below.
Input / Output
Function
O
22kHz enable for QPSK use
O
TS/NPES
O
NVM write-protest
O
Reset for PAL encoder and AV decoder ICs
I
ROM_SIZE, input sense pin
O
Reset for front_end PCB
O
Reset pulse for 18MHz clock gate on front-end PCB
O
Reset for Common Interface ICs
O
Reset for IEEE1394 chip
I
Modem off-hook input
Triggering
Level / edge
Level
Selectable
Selectable
Selectable
Selectable
Selectable
42
Priority
Highest
/\
l
l
\/
Lowest
Werbung
Inhaltsverzeichnis
