Interfaces; Ssi Interface (Bml-S1G0-S; Principle; Data Formats - Balluff BML-S1G0-B7-M5E-0-S284 Serie Betriebsanleitung

BML-S1G0-B/S7_ _-M5E_-_0-(SA26-)S284
Absolute Magnetically Coded Position Measuring System
6

Interfaces

6.1 SSI interface
(BML-S1G0-S...)
The data output of the BML must be loaded
with 120 Ω, otherwise incorrect measurements
may result.
6.1.1

Principle

SSI stands for Synchronous Serial Interface and describes
a digital synchronous interface with a differential clock line
and a differential data line.
With the first falling clock edge (trigger time), the data
word to be output is buffered in the sensor head. Data
output takes place with the first rising clock edge, i.e. the
sensor head supplies one bit to the data line for each rising
clock edge. In doing so, the line capacities and delays of
drivers t when querying the data bits must be taken into
v
account in the controller.
The max. clock frequency f
length (see Technical data on page 30). The t
called monoflop time, is started with the last falling edge
and is output as the low level with the last rising edge. The
data line remains at low until the t
Afterwards, the sensor head is ready again to receive the
next clock package.
Trigger time
Clk
32 bits
SSI Data
32 bits
Trigger time
Clk
24, 25, 26 bits
SSI Data
24, 25, 26 bits
T
Clk
Clk
t
v
Data
Clk
Clock burst
Data
Fig. 6-1: Signals with SSI interface
16 english
is dependent on the cable
clk
time, also
m
time has elapsed.
m
E Null bit Null bit Null bit
t1
Null bit
E MSB
t1
Data
t
v
T
A
6.1.2

Data formats

The sensor head has the following factory settings for
position output, which can no longer be changed
retroactively:
– BML-S1G0-S...: 24, 25, 26, 32 bits, with a maximum
clock frequency f
otherwise 700 kHz.
The above bits include the error and null bits.
– Coded binary or Gray
– Rising or falling
Number of Bit meaning/
bits acc. to sequence
type code
Error Null
breakdown
32 1
26 1
25 1
24 1
Tab. 6-1: SSI resolution, at low resolutions, larger measuring lengths
are possible (see Tab. 9-1 on page 29)
If a position below the start position (section 5.4) is
approached, a negative position value (two's complement)
is output.
Max. sampling rate = clock frequency f
MSB LSB
t2
Data
t m
LSB
t2
T = 1/f
Clk Clk
T = 1/f
A A
n
t = 2 × T
m Clk
t = 150 ns
v
of 1300 kHz at 32 bits,
clk
Max. Clock
measuring frequency
length [m] f
Position
clk
at 1 µm
bit
resolution
3 28 48 70...1300
1 24 8 70...700
1 23 4 70...700
1 22 2 70...700
/(number of bits + 3)
Clk
t m
t t
t
t
t
SSI clock period, SSI clock frequency
Sampling period, sampling rate
Number of bits to be transmitted
(requires n+1 clock impulses)
Time until the SSI interface is ready
again
Transmission delay times (measured
with a 1 m cable)
(kHz)