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Picture in Picture module, PP700
General
The picture in picture module PP700 consists of four sepa-
rate functional sections. These are signal switches icp2
(video) and icp7 (RGB), colour decoder ICp3 (TDA9141) and
baseband delay line ICp4 (TDA4665), analog digital inter-
face for the inserted picture icp5 (SDA9187), and the pic-
ture in picture processor icp6 (SDA9189).
The quarter picture in picture processor SDA9189 enables
four different picture sizes: 1/4, 1/9, 1/16 and 1/36. Also a
so-called multi PIP is possible. This means that there can
be 9 inset pictures on the screen at the same time, 8 of
which are still pictures and 1 is live. The position of the
inset picture can be anywhere on the screen. The features
implemented in the set depend on the software.
Colour decoder, ICp3
The video signal for the inserted picture is taken from the
video matrix switch ICq1 on the main chassis via connec-
tor Xp1 pins 10 (CVBS/Y) and 9 (chroma).
The CVBS signal is fed to the video switch icp2, pin 15 and
output from pin 1 onward to the CVBS input pin 26 of the
colour decoder ICp3.
If the input signal is a Y/C signal, the chroma signal is fed
directly to pin 25 of the colour decoder. The signal path of
the Y signal is same as that of the CVBS signal. The input
mode is chosen via the IIC-bus.
The decoder circuit decodes the CVBS (or Y/C) signal and
generates luminance and colour difference signals. Col-
our difference signals are fed from the output pins 1 and 2
to the baseband delay line ICp4. Delayed colour difference
signals are fed back to the input pins 3 and 4, from where
they are fed via a switch block to output pins 13 (V) and 14
(U). The delayed luminance signal is fed via the same switch
block to output pin 12.
The operation of the colour decoder TDA9141 is very simi-
lar to that of the TDA9143 on the main board.
Analog to digital interface, icp5
The Y, U and V signals are now taken to the A/D-interface
icp5, pins 23 (Y), 21 (U) and 19 (V).The A/D converter con-
verts the analog signals into digital form using 6-bit flash
converters. The digitized Y and UV signals are output from
pins 2...7 (Y) and 8...11 (UV) for the PIP processor.
The white level of the U and V signals is clamped to the
mean value of the Vrefh (pin 22) and Vrefl (pin 20) voltages.
The black level of the Y signal is clamped to the Vrefl volt-
age. The circuit consists of a clock generator which is syn-
chronized to the inserted picture by means of the sandcastle
pulse on pin 15. The clock generator synchronizes the in-
ternal horizontal PLL, which consists of a horizontal timer,
phase comparator, and VCO. The horizontal PLL generates
the line-locked picture in picture system clock LL3 (pin 12)
and internal chip timing. The frequency of the LL3 signal is
13.5 MHz. The RC network on pin 17 filters the output of
the phase comparator. The horizontal timer also determines
the start time and the width of the internal clamping pulse,
as well as the location of the blanking signal BLN (pin 1),
which in turn defines the horizontal duration of the picture
information on the Y output and should be synchronous
with it. Thus the BLN is delayed to the same degree as the
Y signal.
Quarter PIP processor, icp3
The PIP processor contains everything needed in the PIP
function operation blocks, like horizontal and vertical fil-
tering (decimation), field memory, RGB matrix, DA-conver-
sion, clock generation and control circuits.
The video signal of the inset source in a digitized form is
taken from the A/D-interface icp5. The digitized Y signal is
connected to pins 25...30 and the digitized UV signal is taken
to pins 21...24. The input data is first decimated in the in-
put signal processing block. The decimation window, gen-
erated from the inset sync pulses on pins 1 (VSI) and 32
(HSI) and from the detected line standard, has a width of
576 pixels for the luminance signal and 144 pixels for the
chrominance signal. In the vertical direction the window
consists of 252 lines in the 625 lines standard (204 lines in
the 525 lines standard). The size of the inset picture de-
pends on the horizontal and vertical decimation factor. This
factor determines the number of pixels and lines as fol-
lows:
Hor and vert factor
Pixels / line
2 : 1
3 : 1
4 : 1
6 : 1
The decimated data is then written to the field memory.
The frequency of the write clock depends on the decima-
tion factor (6.75 MHz, 4.5 MHz, 3.375 MHz, or 2.25 MHz).
The write clock is divided from the line locked clock (13.5
MHz) on pin 20.
The frequency of the read clock is 27 MHz. The read clock
is generated in the internal oscillator, which is driven by
an external crystal on pins 2 and 3 and line locked to the
horizontal sync pulse (HSP) on pin 15. Synchronization of
the parent channel is performed by the same horizontal
sync pulse (pin 15) and by the vertical sync pulse on pin
16.
From the field memory the data is fed to the output process-
ing block, which determines the position and framing of
the inset picture. A special effect, wipe in / wipe out, is also
available. The inset picture can be programmed, depend-
ing on the software, to appear from (and disappear to) the
lower right corner of the inset picture position.
Finally, the processed data is converted to analog form in
the D/A-converters and signals are output from pins 8 (R),
9 (G) and 10 (B) to the RGB switch, icp7. The fast blanking
signal is output from pin 14 and fed via transistor ttp2 and
onward to the RGB processor on the main board.
Pin 15 (IIC-bus controlled output) of the colour decoder
feeds a high level out, this is fed via transistor ttp3 to the
RGB switch pin 5. A high level on pin 5 selects the input
signals via pins 6, 7 and 8 and onward to the connector
Wp1. If the receiver is equipped with a VGA connector, the
RGB signals are input from connector Xp2, and via RGB
switch pins 2, 3 and 4 to the connector Wp1. Then the volt-
age on the RGB switch pin 5 is low. If the picture in picture
function is used during VGA mode, pin 5 is controlled by
the fast blanking signal via transistor ttp4.
In VGA mode, the software automatically takes care of
ensuring that the RGB Video processor on the main board
is in the right input state.
The FET transistor ttp5 disconnects the serial data line
(SDA) from the PIP processor when the receiver is switched
off. The jumper jp36 is not installed.
Picture in Picture module, PP710
The picture in picture module PP710 is equipped with its
own tuner / IF block in addition to the functions of the PP700.
The IF signal from the PIP tuner is demodulated and am-
plified in ICp1, and fed onward to the video switch icp2,
pin 4. The input selection (pins 9 and 10) is controlled via
tuner pin 4, and is IIC-bus controlled.
Lines / field
288
126
192
84
144
63
96
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