Hardwarebeschreibung
10.4 Ein-/Ausgabeadressbereiche
Bit
Range
11
10:0
TCO Timer Register (TCO_TMR) - Offset 70h
Bit
Range
31:26
25:16
15:0
No Reboot:
PBASE = Bus 0 Device 0x0d Function 1 Reg. 0x10
PM CFG - Power Management Configuration (PMC_CFG) Offset = 0x1008h
NO Reboot = PBASE +PM CFG Offset Bit [4] set to 1
74
Default
Field Name (ID): Description
&
Access
0h
TCO Timer Halt (tco_tmr_halt):
RW
1: The TCO Timer will halt. It will not count, and thus cannot reach a value that
would cause an SMI# or to cause the SECOND_TO_STS bit to be set. This will
also prevent rebooting.
0: The TCO timer is enabled to count. This is the default. This is reset on cold
boot, cold reset, warm reset, and Sx.
0h
Reserved (reserved1): Reserved.
RO
Default
Field Name (ID): Description
&
Access
0h
Reserved (reserved1): Reserved.
RO
4h
TCO Timer Reload Value (tco_trld_val): Value that is loaded into the timer each
time the TCO-RLD register is written. Values of 0000h or 0001h will be ignored
RW
and should not be attempted. The timer is clocked at approximately 0.6
seconds, and thus allows timeouts ranging from 1.2 second to 613.8 seconds.
Note: The timer has an error of +/- 1 tick (0.6s). The TCO Timer will only count
down in the S0 and S0IX state.
0h
Reserved (rsvd): Reserved.
RO
SIMATIC IPC127E
Betriebsanleitung, 11/2019, A5E44296888-AB