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T 22
Tuner
Sicht auf Bestückungsseite / View on Component Side
GRUNDIG Service
Schaltpläne und Druckplattenabbildungen / Circuit Diagrams and Layout of PCBs
IC-Blockdiagramme / IC Block Diagrams
IC 4
SAA6579T
QUAL
1
QUALITY-
BIT
GENERATOR
REGENERATION
16
RDCL
P8 /SEG
65
7
7
P8 /SEG
66
6
6
P8 /SEG
67
5
5
P8 /SEG
68
4
4
P8 /SEG
69
3
3
P8 /SEG
70
2
2
P8 /SEG
71
1
1
P8 /SEG
72
0
0
Vcc
73
V
74
EE
AV
75
SS
V
76
REF
P7 /AN
77
7
7
P7 /AN
78
6
6
P7 /AN
79
5
5
P7 /AN
80
4
4
T 22
RDDA
VREF
MUX
VDDA
VSSA
CIN
SCOUT
2
3
4
5
6
7
8
VP1
DIFFERENTIAL
REFERENZ
DECODER
VOLTAGE
ANTI
57KHZ
BIPHASE
RECONSTRUK.
ALIASING
BANDPASS
SYMBOL
FILTER
FILTER
(8th ORDER)
DECODER
COSTAS LOOP
CLOCKED
VARIABLE AND
COMPARATOR
FIXED DIVIDER
CLOCK
TESTLOGIC AND
OSZILLATOR
SAA6579T
OUTPUT
DEVIDER
AND SYNC
SELEKTOR SWITCH
15
14
13
12
11
10
9
T57
OSCO
OSCI
VDDD
VSSD
TEST
TSTLD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P2
40
0
P2
39
1
P2
38
2
P2
37
3
36
P2
4
P2
35
5
P2
34
6
P2
33
M3817x
7
Vss
32
X
31
OUT
X
30
IN
X
29
COUT
X
28
CIN
RESET
27
P4 /INT
26
0
0
P4 /INT
25
1
1
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Sub
Sub
Clock
Clock
clock
clock
Reset input
input
output
input
output
RESET
X
X
X
X
IN
OUT
CIN
COUT
30
31
28
29
Clock generation
circuit
RAM
ROM
M3817x
A-D converter (8)
PWM (14)
P8 (8)
P7 (8)
P6 (8)
65 66 67 68 69 70 71 72
77 78 79 80 1 2 3 4
75 76
13 14 15 16 17 18
I/O port P8
I/O port P7
I/O port P6
3 - 13
GRUNDIG Service
Schaltpläne und Druckplattenabbildungen / Circuit Diagrams and Layout of PCBs
IC 702
M38172M4-129FP
PIN DESCRIPTION M3817x
Pin
Name
Function
73, 32
V
, V
Power supply
Power supply inputs 4.0 to 5.5V to V
, and 0V to V
.
CC
SS
CC
SS
74
V
Pull-down power input
Applies voltage supplied to pull-down resistors of ports P0, P1, P2 and P3.
EE
76
V
Analog reference voltage
Reference voltage input pin for A-D converter.
REF
75
AV
Analog power voltage
GND input pin for A-D converter. Keep at the same potential as V
SS
SS
27
RESET
Reset input
To reset the microcomputer, this pin should be kept at an "L" level for more than 2µs under high-speed operating conditions.
In low-speed operation start mode, internal reset is not released until the X
30
X
Clock input
Input and output signals for the internal clock generation circuit. It consist of internal feedback amplifier. Connect a ceramic
IN
resonator or quartz crystal between the X
and X
pins to set the oscillation frequency. If an external clock is used,
IN
OUT
31
X
Clock output
connect the clock source to the X
pin and leave the X
pin open. This clock is used as system clock.
OUT
IN
OUT
28
X
Sub clock input
Input and output signals for the internal sub clock generation circuit. It consist of internal amplifier without feedback.
CIN
Connect a ceramic resonator or quartz crystal and external feedback resistor between the X
external clock is used, connect the clock source to the X
pin and leave the X
CIN
29
X
Sub clock output
as the system clock.
COUT
56 - 49
P0
/SEG
/
Output port P0
An 8-bit output port. The output structure is high-
FLD automatic display pins
0
16
DIG
-
breakdown-voltage P-channel open drain with internal
0
P0
/SEG
/
pull-down resistors connected between the output and
7
23
DIG
the V
pin. Are "L" at reset.
7
EE
48 - 41
P1
/DIG
-
Output port P1
An 8-bit output port with the same function as port P0.
FLD automatic display pins
0
8
P1
/DIG
7
15
40 - 33
P2
- P2
I/O port P2
An 8-bit CMOS I/O port. An I/O direction register allows each pin to be individually programmed as either input or output. At
0
7
reset this port is set to input mode. The input levels are TTL compatible.
64 - 57
P3
/SEG
-
Output port P3
An 8-bit output port with the same function as port P0.
FLD automatic display pins
0
8
P3
/SEG
7
15
26
P4
/INT
Input port P4
A 1-bit CMOS input pin.
External interrupt input pin
0
0
0
25 - 22
P4
/INT
-
I/O port P4
A 7-bit CMOS I/O port with the same function as port P2,
External interrupt input pins
1
1
P4
/INT
with CMOS compatible input levels.
4
4
21
P4
5
20, 19
P4
/T1
,
Timer output pins
6
OUT
P4
/T3
7
OUT
12 - 9
P5
/S
,
I/O port P5
An 8-bit I/O port with the same function as port P2. The
Serial I/O1 I/O pins
0
IN1
P5
/S
,
output structure of this port is N-channel open drain, and
1
OUT1
P5
/S
,
the input levels are CMOS compatible.
2
CLK11
P5
/S
/
Keep the input voltage of this port between 0V and V
.
3
RDY1
CC
CS/S
CLK12
8 - 5
P5
/S
,
Serial I/O2 I/O pins
4
IN2
P5
/S
,
5
OUT2
P5
/S
,
6
CLK2
P5
/S
7
RDY2
18
P6
/PWM
I/O port P6
A 6-bit CMOS I/O port with the same function as port P2,
14-bit PWM output pin
0
0
with CMOS compatible input levels.
17
P6
/PWM
8-bit PWM output pin
1
1
16, 15
P6
/CNTR
,
Event counter input pins
2
0
P6
/CNTR 1
3
14, 13
P6
, P6
4
5
4 - 1,
P7
/AN
-
I/O port P7
An 8-bit CMOS I/O port with the same function as port P2,
A-D converter input pins
0
0
80 - 77
P7
/AN
with CMOS compatible input levels.
7
7
72 - 65
P8
/SEG
-
I/O port P8
An 8-bit I/O port with the same function as port P2. The
FLD automatic display pins
0
0
P8
/SEG
output structure of this port is P-channel open drain, and
7
7
the input levels are CMOS compatible. Please note that
this port does not have internal pull-down resistors.
V
V
V
CC
SS
EE
27
73
32
74
Data bus
T1
OUT
Timer 1 (8)
CPU
A
CNTR
0
Timer 2 (8)
X
T3
Y
OUT
Timer 3 (8)
SI/O
S
automatic
Timer 4 (8)
transfer
PC
PC
H
L
CNTR
1
controller
PS
Timer 5 (8)
PWM
OUT
Timer 6 (8)
Local data bus
SI/O2 (8)
SI/O1 (8)
P5 (8)
P4 (8)
P3 (8)
P2 (8)
5 6 7 8 9 10 11 12
19 20 21 22 23 24 25 26
57 58 59 60 61 62 63 64
33 34 35 36 37 38 39 40
I/O port P5
I/O port P4
Output port P3
I/O port P2
Alternate Function
.
- X
clock has had time to stabilize.
CIN
COUT
and X
pins. If an
CIN
COUT
pin open. This clock can also be used
COUT
SI/O
FLD
FLD
automatic
automatic
automatic
transfer
display
display
RAM
controller
RAM
32 bytes
48 bytes
P1 (8)
P0 (8)
41 42 43 44 45 46 47 48
49 50 51 52 53 54 55 56
Output port P1
Output port P0
3 - 14
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