Recommended Accessories; Appendix; List Of Figures - R&S HM8143 Benutzerhandbuch

Modulation Input (CH1, CH3)
Rear connectors
Input level
Accuracy
Modulation bandwidth
Trigger Input (BNC)
Function
Trigger level
Edge direction
Arbitrary Function (CH1)
Parameter
Number of Points
Dwell time
Repetition rate
Resolution
Trigger
Remote Interfaces
Standard
Optional
Miscellaneous
Input power option
Power consumption
Mains fuses
115 V
AC
230 V
AC
Operating temperature
Storage temperature
Humidity
Display
Dimensions (H x W x D)
Rack mount capability
(19" rack mount kit, 2RU)
Weight
The specifications are based on a 30 min warm-up period.
Accessories included:
Line cord, operating manual

Recommended accessories:

HZ42 19" rackmount kit, 2 RU
HZ10S 5 x silicon test lead (black)
HZ10R 5 x silicon test lead (red)
HZ10B 5 x silicon test lead (blue)
HO880 IEEE-488 (GPIB) interface card
Specifi cations
2x BNC
0 V to 10 V
1 % of full scale
DC to 20 kHz
Triggering the arbitrary function
TTL
rising, falling
Voltage, dwell time
max. 4,096
100 µs to 60 s
continous or burst mode with 1 to 255
repetitions
12 Bit
interface, trigger input
Dual interface RS-232 / USB (HO820)
IEEE-488 (GPIB) interface (HO880)
115 V / 230 V (±10 %), 50 Hz to 60 Hz,
AC AC
CAT II
300 VA
2x 6 A, slow blow (5 mm x 20 mm)
2x 3.15 A, slow blow (5 mm x 20 mm)
+5 °C to +40 °C
-20 °C to +70 °C
5 % to 80 %
4x 4 digits, 7-segment LEDs
75 x 285 x 365 mm
Yes (HZ42)
9 kg

10 Appendix

10.1 List of figures
Fig. 1.1: Voltage selector for HM8143 . . . . . . . . . . . . . . . . .26
Fig. 1.2: Product labeling in accordance with EN 50419 . .27
Fig. 2.1: Front panel of the HM8143 . . . . . . . . . . . . . . . . . .28
Fig. 2.2: Rear panel of the HM8143 . . . . . . . . . . . . . . . . . . .29
Fig. 3.1: Linear power supply . . . . . . . . . . . . . . . . . . . . . . . .29
Fig. 3.2: Primary switched-mode power supply . . . . . . . . .29
Fig. 3.3: Socondary switched-mode power supply . . . . . . .29
Fig. 3.4: The load of a switch mode powersupply . . . . . . . .30
Fig. 3.5: Series operation . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Fig. 3.6: Parallel operation . . . . . . . . . . . . . . . . . . . . . . . . . .30
Fig. 3.7: Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Fig. 4.1: Compensating the voltage drops in diagram . . . .31
Fig. 8.1: Display of channel I in arbitrary mode . . . . . . . . . .37
1
Appendix
39